High performance integrated circuits have gained wide acceptance and utility in present day electronic devices that utilize high data applications. In addition, however, there is a great demand for shrinking these microelectronic devices to provide an increased device density on the microelectronic chip and provide chips that are faster, but at the same time, consume less power to conserve and extend battery life. In fact, to provide the required device performance, the scaling of the gate dielectric thickness in these devices has now reached below 2.0 nm in the core or low voltage regions, while the dielectric thickness in the input/output (I/O) regions is 2.0 nm or greater.
However, simply scaling standard dielectrics while maintaining good process control in this thickness regime is very difficult. Thus, the industry is left with the desire to use thicker films that are correspondingly easier to control to tight limits, while decreasing the electrical dielectric thickness to increase device performance (increase drive current or IDS) with less leakage and without degradation to long channel threshold voltages.
To achieve these goals, the industry has turned to the use of higher dielectric constant materials. One such material that has found popular utility is nitrogen, which may be incorporated using a de-coupled plasma nitridation process or DPN process. In such processes, plasma nitridation is used to incorporate a dielectric with a uniformly high dose of nitrogen. The addition of this nitrogen effectively increases the dielectric constant value of the gate dielectric, thus allowing a physically thicker film to be electrically thinner. In other words, a smaller equivalent oxide thickness (EOT) is achieved. The presence of the nitrogen in the gate oxide also blocks boron penetration, which prevents the boron from getting into the channel region and which could further affect device performance.
This conventional nitridation process works well in achieving a fairly uniform nitrogen profile in the low voltage or core regions of the device where the gate dielectric thickness is below 2 nm. Uniform nitrogen profile across the thickness of the dielectric is highly desirable from a reliability perspective. A non-uniform nitrogen depth profile causes spatially non-uniform trap generation and thereby higher number of time dependent dielectric breakdowns (TDDB) or lower mean time to failure. However, in the I/O regions where the dielectric thickness is at 2 nm or greater, the nitrogen profile is not uniform in that the nitrogen can pile up at the upper surface of the gate dielectric, which results in a non-uniform nitrogen profile. A non-uniform nitrogen profile in the I/O region creates serious reliability issues with the operation of the microelectronic devices in that it may cause premature breakdown of the gate dielectric.
As the microelectronics industry continues to improve its process technologies, controlling or reducing the amount of leakage associated with these transistors in both the core region and the I/O region becomes increasingly difficult. Further, the amount of leakage associated with a transistor during its use has experienced a growing concern within the microelectronics industry. Concern over this issue has increased as the desire to extend the battery life used in electronic communication devices has also become of greater importance.
Thus, while the increase of the nitrogen in the gate oxide allows smaller EOTs to be achieved and is substantially uniform in the core region of the device, the non-uniformity of the nitrogen profile in the I/O region and the dielectric reliability issues associated therewith is a growing problem as expectations of device performance continues to increase.
Accordingly, what is needed in the art is a nitridation process that overcomes the deficiencies discussed above.